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Bug #65791

open

Enable Ceph to benefit from a faster CRC32 implementation

Added by Tyler Stachecki 15 days ago. Updated 13 days ago.

Status:
New
Priority:
Normal
Assignee:
-
Category:
librados
Target version:
-
% Done:

0%

Source:
Tags:
Backport:
Regression:
No
Severity:
3 - minor
Reviewed:
Affected Versions:
ceph-qa-suite:
Pull request ID:
Crash signature (v1):
Crash signature (v2):

Description

ISA-L, a component in Ceph (https://github.com/ceph/isa-l/tree/bee5180a1517f8b5e70b02fcd66790c623536c5d) provides multiple CRC32 implementations. To date, Ceph has only used the lowest common denominator of these implementations (crc32_iscsi_00), which runs on all CPUs which provide the CRC32C instruction.

There is an alternative implementation which leverages SSE4.1 (PCLMULQDQ - carryless vectorized multiplication) to provide a much more efficient, faster implementation for CPUs which provide the SSE4.1 instruction set. A whitepaper for this implemenation of CRC32 can be found here: https://fossies.org/linux/zlib-ng/doc/crc-pclmulqdq.pdf

This instruction came to be in 2008 (Westmere), and as such is now quite ubiquitous -- meaning that if we add support for this CRC32 implementation, the vast majority of Ceph users stand to benefit to some degree.

Actions #1

Updated by Tyler Stachecki 13 days ago

Small correction to the above -- this should be the PCLMUL instruction set, and not SSE4.1.

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